Failure to observe this limitation a frequent source of errors in digital circuits. 212, the master-slave flip-flop here ca only change state once and cannot change back, as one of the two input NAND gates is always disabled by the feedback. This is because, unlike the RS master-slave flip-flop in Fig. 2.14 only applies if the state at the JK inputs remains unchanged as long as clock C is 1. However, because of the feedback, operation of the JK flip-flop is subject to an important limitation: the truth table in Fig. 2.15 - JK master-slave flip-flop as flip-flop after a (010) clock cycle. 2.14 - Output state of a JK master-slave Fig. Consequently, JK master-slave flip-flops provide a particularly simple means of constructing counters.įig. This is the same as dividing the frequency by two, as Fig. 10.12 that the output state for J = K = 1 is inverted at each clock pulse. The external inputs are then designated J and K respectively. The feedback circuit shown in heavy type in Fig. In order to be able to make use of this input combination, the complementary output data are additionally applied to the input gates. The input combination R = S = 1 necessarily results in an undefined behavior, because inputs, in the master simultaneously go from 00 to 11 when clock C goes to 0. Data transmission therefore occurs on the negative-going edge how-ever, there is no clock state in which the input data have a direct effect on the output, as is the case with transparent flip-flops. The slave is simultaneously triggered, thus transferring the state of the master to the output. When the clock goes to 0, the master is disabled, thereby freezing the state present immediately prior to the negative-going edge of the clock signal. The output state remains unchanged, because the slave is disabled. As long as clock C = 1, the input information is read into the master. The two flip-flops are mutually inhibited by complementary clock signals. It consists of two statically clocked RS flip-flops of the type shown in Fig.
They therefore comprise two flip-flops: the master flip-flop at the input and the slave flip-flop at the output.įigure 2.12 shows a master-slave flip-flop of this kind. In these cases flip-flops are required which temporarily store the input state and only transfer it to the output when the inputs are inhibited once more.
For many applications, such as counters and shift registers, transparent flip-flops are unsuitable.
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